[Nand2Tetris] Project 1 流水账

实验要求以与非门(Nand)为基础搭建 15个逻辑门分别为:NotAndOrXorMuxDMuxNot16And16Or16Mux16Or8WayMux4Way16Mux8Way16DMux4WayDMux8Way代码实现NotCHIP Not { IN in; OUT out; PARTS: Nand(a in, b in, out out); }AndCHIP And { IN a, b; OUT out; PARTS: //// Replace this comment with your code. Nand(a a, b b, out prt); Nand(a prt, b prt, out out); }OrCHIP Or { IN a, b; OUT out; PARTS: Not(in a, out Na); Not(in b, out Nb); And(a Na, b Nb, out out1); Not(in out1, out out); }XorCHIP Xor { IN a, b; OUT out; PARTS: Not(in a, out Na); Not(in b, out Nb); And(a a, b Nb, out res1); And(a Na, b b, out res2); Or(a res1, b res2, out out); }MuxCHIP Mux { IN a, b, sel; OUT out; PARTS: Not(in sel, out Nsel); And(a a, b Nsel, out res1); And(a b, b sel, out res2); Or(a res1, b res2, out out); }DMuxCHIP DMux { IN in, sel; OUT a, b; PARTS: Not(in sel, out Nsel); And(a in, b Nsel, out a); And(a in, b sel, out b); }Not16CHIP Not16 { IN in[16]; OUT out[16]; PARTS: Not(in in[0], out out[0]); Not(in in[1], out out[1]); Not(in in[2], out out[2]); Not(in in[3], out out[3]); Not(in in[4], out out[4]); Not(in in[5], out out[5]); Not(in in[6], out out[6]); Not(in in[7], out out[7]); Not(in in[8], out out[8]); Not(in in[9], out out[9]); Not(in in[10], out out[10]); Not(in in[11], out out[11]); Not(in in[12], out out[12]); Not(in in[13], out out[13]); Not(in in[14], out out[14]); Not(in in[15], out out[15]); }And16CHIP And16 { IN a[16], b[16]; OUT out[16]; PARTS: //// Replace this comment with your code. And(a a[0], b b[0], out out[0]); And(a a[1], b b[1], out out[1]); And(a a[2], b b[2], out out[2]); And(a a[3], b b[3], out out[3]); And(a a[4], b b[4], out out[4]); And(a a[5], b b[5], out out[5]); And(a a[6], b b[6], out out[6]); And(a a[7], b b[7], out out[7]); And(a a[8], b b[8], out out[8]); And(a a[9], b b[9], out out[9]); And(a a[10], b b[10], out out[10]); And(a a[11], b b[11], out out[11]); And(a a[12], b b[12], out out[12]); And(a a[13], b b[13], out out[13]); And(a a[14], b b[14], out out[14]); And(a a[15], b b[15], out out[15]); }Or16CHIP Or16 { IN a[16], b[16]; OUT out[16]; PARTS: Or(a a[0], b b[0], out out[0]); Or(a a[1], b b[1], out out[1]); Or(a a[2], b b[2], out out[2]); Or(a a[3], b b[3], out out[3]); Or(a a[4], b b[4], out out[4]); Or(a a[5], b b[5], out out[5]); Or(a a[6], b b[6], out out[6]); Or(a a[7], b b[7], out out[7]); Or(a a[8], b b[8], out out[8]); Or(a a[9], b b[9], out out[9]); Or(a a[10], b b[10], out out[10]); Or(a a[11], b b[11], out out[11]); Or(a a[12], b b[12], out out[12]); Or(a a[13], b b[13], out out[13]); Or(a a[14], b b[14], out out[14]); Or(a a[15], b b[15], out out[15]); }Mux16CHIP Mux16 { IN a[16], b[16], sel; OUT out[16]; PARTS: Mux(a a[0], b b[0], sel sel, out out[0]); Mux(a a[1], b b[1], sel sel, out out[1]); Mux(a a[2], b b[2], sel sel, out out[2]); Mux(a a[3], b b[3], sel sel, out out[3]); Mux(a a[4], b b[4], sel sel, out out[4]); Mux(a a[5], b b[5], sel sel, out out[5]); Mux(a a[6], b b[6], sel sel, out out[6]); Mux(a a[7], b b[7], sel sel, out out[7]); Mux(a a[8], b b[8], sel sel, out out[8]); Mux(a a[9], b b[9], sel sel, out out[9]); Mux(a a[10], b b[10], sel sel, out out[10]); Mux(a a[11], b b[11], sel sel, out out[11]); Mux(a a[12], b b[12], sel sel, out out[12]); Mux(a a[13], b b[13], sel sel, out out[13]); Mux(a a[14], b b[14], sel sel, out out[14]); Mux(a a[15], b b[15], sel sel, out out[15]); }Or8WayCHIP Or8Way { IN in[8]; OUT out; PARTS: Or(a in[0], b in[1], out or1); Or(a in[2], b in[3], out or2); Or(a in[4], b in[5], out or3); Or(a in[6], b in[7], out or4); Or(a or1, b or2, out res1); Or(a or3, b or4, out res2); Or(a res1, b res2, out out); }Mux4Way16CHIP Mux4Way16 { IN a[16], b[16], c[16], d[16], sel[2]; OUT out[16]; PARTS: Mux16(a a, b b, sel sel[0], out m1); Mux16(a c, b d, sel sel[0], out m2); Mux16(a m1, b m2, sel sel[1], out out); }Mux8Way16CHIP Mux8Way16 { IN a[16], b[16], c[16], d[16], e[16], f[16], g[16], h[16], sel[3]; OUT out[16]; PARTS: Mux4Way16(aa , bb , cc , dd , selsel[0..1] , outm1 ); Mux4Way16(ae , bf , cg , dh , selsel[0..1] , outm2 ); Mux16(am1,bm2,selsel[2],outout); }DMux4WayCHIP DMux4Way { IN in, sel[2]; OUT a, b, c, d; PARTS: Not(in sel[1],outNsel1); And(ain , b Nsel1, outin1 ); And(ain , b sel[1], outin2 ); DMux(inin1 , selsel[0] , aa , bb ); DMux(inin2 , selsel[0] , ac , bd ); }DMux8WayCHIP DMux8Way { IN in, sel[3]; OUT a, b, c, d, e, f, g, h; PARTS: Not(in sel[2], outNsel2 ); And(a Nsel2, b in, out in1); And(a sel[2], b in, out in2); DMux4Way(in in1, sel sel[0..1], a a, b b, c c, d d); DMux4Way(in in2, sel sel[0..1], a e, b f, c g, d h); }心得感想有数字电路基础的做起来还是比较容易可以不用刷视频就能完成所有题目。当然后面也有稍微卡住一会比如做DMux8Way的时候一直没有头绪前面实现Or门的时候还好记得之前学过的摩尔定律不然可能一时半会也解不出来。