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参考

cocotb文档

iverilog 配合 Makefile 搭建 Verilog 仿真工程

ModelSim 配合 Makefile 搭建 Verilog 仿真工程

目录结构

tree /f D:. ├─rtl │ adder.v │ └─sim │ Makefile │ test_adder.py

文件

rtl/adder.v

module adder ( input wire clk, input wire rst, input wire [7:0] a, input wire [7:0] b, output reg [8:0] sum ); always @(posedge clk) begin if (rst) sum <= 9'd0; else sum <= a + b; end endmodule

sim/Makefile

TOPLEVEL_LANG=verilog SIM=icarus TOPLEVEL=adder MODULE=test_adder WAVES=1VERILOG_SOURCES=../rtl/adder.v include$(shell cocotb-config--makefiles)/Makefile.sim .PHONY: wave wave: gtkwave sim_build/adder.fst

sim/test_adder.py

importcocotbfromcocotb.clockimportClockfromcocotb.triggersimportRisingEdge,Timer,ReadOnly,Firstfromcocotb.utilsimportget_sim_time@cocotb.test()asyncdeftest_adder(dut):# =========================================================# 时钟# =========================================================cocotb.start_soon(Clock(dut.clk,10,unit="ns").start())# =========================================================# 信号监视器（输入/输出变化即打印）# =========================================================asyncdefwatch():last=NonewhileTrue:# 等待任一信号变化awaitFirst(dut.rst.value_change,dut.a.value_change,dut.b.value_change,dut.sum.value_change,)# 等下个上升沿awaitRisingEdge(dut.clk)# 进入 ReadOnly，保证值稳定awaitReadOnly()now=(int(dut.rst.value),int(dut.a.value),int(dut.b.value),int(dut.sum.value),)ifnow!=last:t=int(get_sim_time("ns"))# cocotb 2.x 是 float，必须转 intdut._log.info(f"[{t:6d}ns] "f"rst={now[0]}"f"a={now[1]:3d}"f"b={now[2]:3d}"f"sum={now[3]:3d}")last=now cocotb.start_soon(watch())# =========================================================# 复位# =========================================================dut.rst.value=1dut.a.value=0dut.b.value=0# 等20nsawaitTimer(20,"ns")awaitRisingEdge(dut.clk)dut.rst.value=0# =========================================================# 测试向量# =========================================================tests=[(1,2),(10,20),(100,23),(255,1),]fora,bintests:dut.a.value=a dut.b.value=b# a/b 在这一拍被采样awaitRisingEdge(dut.clk)# sum 在下一拍稳定awaitRisingEdge(dut.clk)assertint(dut.sum.value)==a+b,\f"{a}+{b}!={int(dut.sum.value)}"# 再跑一点时间，方便看波形awaitTimer(20,"ns")

命令

安装 Python 依赖

pipinstallcocotb

编译

如果在windows里,下面的命令应在git bash

PC@ming MINGW64 /d/workspace/gitee/0/ming-verilog_prj/ming-verilog/test/proj/sim(master)$makerm-fresults.xml"D:/Program Files (x86)/Dev-Cpp/mingw32/bin/make"-fMakefile results.xml make[1]: Entering directory'D:/workspace/gitee/0/ming-verilog_prj/ming-verilog/test/proj/sim'/d/soft/iverilog/bin/iverilog-osim_build/sim.vvp-sadder-g2012-fsim_build/cmds.f-scocotb_iverilog_dump../rtl/adder.v sim_build/cocotb_iverilog_dump.v D:/soft/Anaconda3/envs/platformio/Lib/site-packages/cocotb_tools/makefiles/simulators/Makefile.icarus:66: Using MODULE is deprecated, please use COCOTB_TEST_MODULES instead.rm-fresults.xmlCOCOTB_TEST_MODULES=test_adderCOCOTB_TESTCASE=COCOTB_TEST_FILTER=COCOTB_TOPLEVEL=adderTOPLEVEL_LANG=verilog\/d/soft/iverilog/bin/vvp-MD:/soft/Anaconda3/envs/platformio/Lib/site-packages/cocotb/libs-mcocotbvpi_icarus sim_build/sim.vvp-fst-.--ns INFO gpi..mbed\gpi_embed.cpp:94in_embed_init_python Using Python3.11.9 interpreter at D:/soft/Anaconda3/envs/platformio/python.exe Could notfindplatform dependent libraries<exec_prefix>-.--ns ERROR gpi..mbed\gpi_embed.cpp:155in_embed_init_python Unexpected sys.executable value(expected'D:/soft/Anaconda3/envs/platformio/python.exe', got'D:\soft\iverilog\bin\vvp.exe')-.--ns INFO gpi..\gpi\GpiCommon.cpp:79ingpi_print_registered_impl VPI registered0.00ns INFO cocotb Running on Icarus Verilog version10.1(stable)0.00ns WARNING gpi vpi_iterate returned NULLfortypevpiInstanceforobject NULL0.00ns INFO cocotb Seeding Python random module with17674921130.00ns INFO cocotb Initialized cocotb v2.0.1 from D:\soft\Anaconda3\envs\platformio\Lib\site-packages\cocotb0.00ns INFO cocotb.regression pytest not found,installit toenablebetter AssertionError messages0.00ns INFO cocotb Running tests0.00ns INFO cocotb.regression running test_adder.test_adder(1/1)FST info: dumpfile sim_build/adder.fst openedforoutput.0.00ns INFO cocotb.adder[0ns]rst=1a=0b=0sum=030.00ns INFO cocotb.adder[30ns]rst=0a=1b=2sum=350.00ns INFO cocotb.adder[50ns]rst=0a=10b=20sum=3070.00ns INFO cocotb.adder[70ns]rst=0a=100b=23sum=12390.00ns INFO cocotb.adder[90ns]rst=0a=255b=1sum=256120.00ns INFO cocotb.regression test_adder.test_adder passed120.00ns INFO cocotb.regression ************************************************************************************** ** TEST STATUS SIM TIME(ns)REAL TIME(s)RATIO(ns/s)** ************************************************************************************** ** test_adder.test_adder PASS120.000.0040012.44** ************************************************************************************** **TESTS=1PASS=1FAIL=0SKIP=0120.000.0120002.24** **************************************************************************************

看波形

$makewave gtkwave sim_build/adder.fst GTKWave Analyzer v3.3.71(w)1999-2016 BSI FSTLOAD|Processing5facs. FSTLOAD|Built5signals and0aliases. FSTLOAD|Building facility hierarchy tree. FSTLOAD|Sorting facility hierarchy tree.

清空编译

$makeclean