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module tb_s2p();reg clk;reg rstn;reg en;reg din;wire [7:0] dout;parameter CLK_PERIOD = 20;initial begin$display("---------------------------");$display("[%0t] TB_INFO: Simulation Started.", $time);$display("---------------------------");initialize_signals();apply_reset();apply_en();send_data(8'hff);#40send_data(8'h0b);$diaplay("---------------------------");$display("[%0t] TB_INFO: Test finish! Simulation Stopped.", $time);$diaplay("---------------------------"); #40$finish; endtask initialize_signals;begindin <= 1'b0;endendtasktask apply_reset;begin$display("[%0t] TB_INFO: Apllying hardware reset...", $time);rstn <= 1'b0;#(CLK_PERIOD * 5);rstn <= 1'b1;#(CLK_PERIOD);$display("[%0t] TB_INFO: Hardware reset released.", $time);endendtasktask apply_en;beginen <= 1'b0;#(CLK_PERIOD * 2);en <= 1'b1;endendtasktask send_data;input [7:0] data_to_send;integer i;begin$display("[%0t] TB_INFO: Send data...0x%h", $time, data_to_send);@(posedge clk);din <= 1'b0;@(posedge clk);for(i=0; i<8;i++)begindin <= data_to_send[i];@(posedge clk);enddin <= 1'b0;#CLK_PERIOD;endendtask`ifdef FSDBinitial begin$fsdbDumpfile("waveform.fsdb");$fsdbDumpvars;end`elsif VCDPLUSinitial begin$vcdplusfile("waveform.vpd");$vcdpluson;end`endifs2p u_s2p(.clk (clk ),.rstn (rstn),.en (en ),.din (din ),.dout (dout) );endmodule
主要是使用task函数send_data,发送一串数据